The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
During fabrication, integrated circuits are subjected to various electrical and functional tests. For example, one test technique is known as scan-based testing in which flip- flops of the integrated circuit are configured in a test mode to function as one or more shift registers (also referred to as “scan chains”). In the test mode, one or more test patterns of bits are shifted through the scan chain with a resulting pattern indicative of how the die operates in response to the test patterns being output at a terminus of the scan chain.